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投递邮箱：nahu@nvidia.com

职位简介：
·    与design工作密切挂钩
·    能更全面的了解chip生产过程中从前端到后端的整个过程
·    接触所有相关team，能扩宽知识领域及对应skill sets，锻炼全面
·    对chip的贡献更直观：design→how to make better design
·    Careerpath: 接触到chip生产的所有流程，可以真正了解自己的兴趣所在
→EDAtools
→Verification
→Backend
→Power
Shanghaipower team is responsible for researching power expenditures and workl
oadefficiency to identify architectural, micro-architectural strategies for po
weroptimization. We want to hire promising talent who can handle project(s)ind
ividually/collectively and also add new dimension to the team.
Responsibilities:
·    Create a methodology/algorithm to evaluate power efficiency on high-l
evel(architecture) designs.
·    Support IP designers using the power flow to do the power scrubbingwo
rk and improve their power efficiency on micro-arch (ASIC) level.
·    Understand and perform block level and chip-level power analysis.
·    Communicate/Cooperate with local and abroad teams with power-relatedp
rojects.
·    Co-work with power ARCH team/IP team to evaluate new low-power techno
logiesand improve chip power efficiency.
Requirements:
·    MSEE/MSCS postgraduate.
·   Experience in ASICdesign/verification, low power knowledge is a strong
plus.
·    Must befamiliar with at least one of the programming languages, C/C++
(preferred), Python,Perl.
·    Excellent English writing/speaking skills are desired.
·   Good communication skills.